1. Field of the Invention
The present invention relates to a semiconductor device/circuit having at least partially crystallized semiconductor layer and a manufacturing method thereof. The semiconductor device/circuit manufactured according to the present invention is formed on any of insulation substrates such as glass substrates and semiconductor substrates such as single crystal silicon substrates. In particular, the present invention relates to a semiconductor device/circuit having a thin film transistor (TFT) and/or a thin film diode (TFD) (for example, image sensor) manufactured by way of crystallization (activation) through heat annealing.
2. Description of the Prior Art
Thin film semiconductor devices such as TFT and TFD are classified into amorphous devices and crystalline devices depending on the crystalline structures of the semiconductor materials used. Amorphous silicon can be fabricated at a low temperature and shows excellent mass productivity. However, it is inferior to crystalline silicon in view of physical properties such as field effect mobility or conductivity. So it has been demanded for crystalline semiconductor devices in order to obtain hiEh speed characteristics. On the other hand, it has been known that amorphous semiconductors are usable, for example, to light sensors since they generally show large change in the photoconductivity. It has been proposed recently a circuit for driving a light sensor using an amorphous silicon diode or a thin film diode by a thin film transistor using crystalline silicon capable of high speed operation ( for example, integrated image sensor circuit).
FIGS. 1A-1E show an example for the steps of fabricating a circuit comprising a combination of an amorphous silicon diode and a crystalline silicon TFT in the prior art. An underlying insulation film 51 is formed on a glass substrate 50, over which an amorphous silicon film is formed and crystallized by applying long time annealing at a temperature higher than 600.degree. C. Then, it is patterned to obtain an island-like silicon region 52. Then, a gate insulation film 53 is formed and, further, gate electrodes 54N and 54P are formed (refer to FIG. 1A).
Then, an N-type impurity region 55N and a p-type impurity region 55P are formed by using known CMOS fabrication technique. In this impurity introduction step, an impurity element is introduced into a semiconductor layer with a gate electrode as a mask in a self-aligning manner. After the implantation of impurities, the impurities are activated by laser annealing, heat annealing or like other means (refer to FIG. 1B).
Then, a first interlayer insulator 58 is formed through which contact holes are formed, thereby forming electrode/wiring 57a, 57b, 57c for source and drain of TFT, and an electrode 57d for an amorphous silicon diode (FIG. 1C).
Then, p-, I- (intrinsic) and N-type amorphous silicon films 58P, 58I and 58N are successively laminated, which are then patterned to form a diode junction portion (FIG. 1D).
Finally, a second interlayer insulator 59 is formed through which contact holes are formed thereby forming an electrode 60 of the amorphous silicon diode to complete a circuit (FIG. 1E).
In the prior art method requiring such procedures, it is necessary to form silicon films 52, 58I and the interlayer insulators 56, 59 each by two layers, which requires film formation for long time and, in addition, the N-type layer 58N and the p-type layer 58P have to be formed. Therefore, it involves a problem that the throughput is reduced. Further, a plasma CVD or vacuum CVD process used for forming such films, takes much dead time for the maintenance of the apparatus and the presence of such additional step further reduces the throughput.
Furthermore, since crystallization of the silicon film used in the crystalline silicon TFT also requires a temperature higher than 600.degree. C. and needs a time as much as 24 hours or longer for crystallization, many facilities for crystallization apparatus are required in actual mass production, which results in enormous installation cost.